1. Field of the Invention
The present invention relates to a method for improving the intermediate dielectric profile, particularly for non-volatile memories such as EPROMs and FLASH memories.
2. Discussion of the Related Art
The gradual reduction in the size of chips allows an increasingly larger number of devices to be located on each individual silicon wafer, with a consequent reduction in production costs.
In reducing memory size more and more, an increasingly important role is played by the space occupied by each individual memory cell, which is repeated in an array millions of times in a matrix until the desired memory capacity is reached.
The ever greater size reduction, on the other hand, causes many problems in the connection and continuity of the metal lines. Elevation differences in the devices and size reduction (reduction in the size of the contacts and of the metal lines, reduction in the distances between the contact and the gate terminal of the cell and of the distances between metal lines) can cause elevation differences that are difficult to span adequately with the interconnecting metal layers.
In order to improve contact formation, deposition methods (doped dielectrics) and reflow methods, i.e., thermal treatments for redistributing the dielectric and thus "soften" the elevation differences, have been developed.
The method normally used to produce memories entails the use of memory cells with implantations that are self-aligned with respect to the gate terminal of the cell, in order to ensure the electrical performance (writing of the memory cell), and transistors, with structures of the LDD (Low Doped Drain) type, used to relax the electrical fields.
A method that is currently used to provide LDD structures is the generation of wings made of oxide, generally termed oxide "spacers", that are formed by means of a process for depositing a non-doped dielectric and with an RIE etching (anisotropic etching in plasma) that leaves an oxide residue at the sides of the transistor gates.
Light implantations are performed before generating the oxide spacers, while heavy source/drain implantations, self-aligned with the spacers, are performed; the two implantations are of the same type: phosphor (light) and arsenic (heavy) for the N-channel transistors, and low-dose boron (light) and high-dose boron (heavy) for P-channel transistors.
FIG. 3 is a sectional view of a memory cell, of an N-channel transistor, and of a P-channel transistor. In particular, the element on the left in the figure is the memory cell, the central element is the N-channel transistor, and the element on the right is the P-channel transistor.
In detail, the reference numeral 1 designates the N-type substrate, the reference numeral 2 designates the N-type well, the reference numeral 3 designates the gate oxide layer, and the reference numeral 4 designates the layer of oxide present between the two layers of conducting polysilicon 11 and 12 of the memory cell. The polysilicon layer 12 is the control gate terminal of both the memory cell and the transistors, whereas the polysilicon layer 11 is the floating gate terminal in which charge accumulation occurs.
Between one device and the next (memory cell--N-type transistor--P-type transistor) there is provided a layer of field oxide 5 that acts as an insulator. A junction 6 is present, for the memory cell, adjacent to the field oxide 5 and is self-aligned with the gate terminal of the cell.
Likewise, adjacent to the transistors (N and P) there are provided light implantations of the LDD type, designated respectively by the reference numerals 7 and 10 for the N-channel transistors and for the P-channel transistors, as well as source/drain junctions that are self-aligned with the oxide wings 13 of the devices and are designated by the reference numerals 8 and 9 respectively.
The oxide wings, i.e., the spacers, are designated by the reference numeral 13.
A method known as SAS (Self Align Source) is currently used to selectively remove the spacers 13 on the source terminal side. In order to better understand the differences of the known SAS method with respect to the conventional method for producing memory cells, it is convenient to describe the two methods side by side, in order to point out their drawbacks that cause the need for a new solution to the problem.
FIGS. 1 and 4 show, for the standard process and for the SAS process, the first step of the process, which in one case (standard process, FIG. 1) consists in forming the region of the source line by means of an appropriate mask and in the other case (SAS method, FIG. 4) consists in forming the active drain area regions. In this manner, in the second case bands of active drain area 15 and bands of field oxide 14 (which is insulating, previously designated in FIG. 3 with the reference numeral 5) are obtained, that run uninterruptedly along the entire length of the matrix.
Then the word lines 16 are formed by means of the mask for the deposition of polysilicon.
A heavy doping implantation of the drain and source areas of the cells is then performed for both processes.
Then a step of oxide deposition (formation of the spacers 13) with RIE etching is performed.
At this point, the SAS process entails an additional SAS mask that is shown in FIG. 6 and designated by the reference numeral 17, to open only the source line regions (which are still not open with this process, differently from the standard process).
The SAS mask 17 is then arranged approximately halfway between the two word lines 16, allowing to provide the opening in the resist and to remove the field oxide bands 14 in the source line 18.
The areas of the source line that have thus been exposed are doped at this point by ion implantation.
FIG. 8 is a plan view of the final structure of the cell, executed by means of the SAS process, inserted in the matrix of an EPROM memory. In this figure, the reference numeral 18 designates the source line, the reference numeral 15 designates the active drain area, and the reference numeral 30 designates the metal bit line.
By means of the SAS process it is thus possible to remove the oxide spacers on the source line side.
FIG. 7 is a sectional view of memory cells in which the spacers are removed selectively, by means of the SAS matrix, from the word lines 16, on the side of the sources 18.
Although the SAS technique is advantageous with respect to the execution of a memory cell with the standard process, the cell thus formed has the drawback that it still has spacers on the drain side.
A principal aim of the present invention is therefore to provide a method for improving the intermediate dielectric profile that allows a reduction in the problems related to the deposition of the metal contact layers.
Within the scope of this aim, an object of the present invention is to provide a method for improving the intermediate dielectric profile so as to reduce the elevation differences of the devices, accordingly avoiding the danger of a reduction in the thickness of the layers that are deposited subsequently (metal layers for connection and final passivation).
Another object of the present invention is to provide a method for improving the intermediate dielectric profile that can be applied to memory cells produced both with the standard process and with the SAS (Self Align Source) process.
Another object of the present invention is to provide a method for improving the intermediate dielectric profile that allows, at the same time, to reduce a step for heavy source/drain ion implantation in the memory matrix.
Another object of the present invention is to provide a method for improving the intermediate dielectric profile that at the same time allows to eliminate the problems linked to the possible misalignment of the contacts and to the consequent reduction in the width of the field oxide, with insulation problems.
Another object of the present invention is to provide a method that is highly reliable and relatively easy to perform at competitive costs.